Technical Staff Engineer - Design

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Job Description: Microchip Technology's MCU Business Unit is at the forefront of Edge AI innovation, delivering production-ready, full-stack solutions that bring intelligent real-time decision-making to industrial, automotive, data center, and consumer IoT networks .   We are seeking an experienced   Technical Staff Engineer   to drive chiplet-based architecture definition and advanced-node product research for our next-generation microcontrollers. This senior-level role will work closely with the   other   business unit s   and cross-functional teams to align chiplet definitions with platform, technology, and product requirements.   As chiplet technology revolutionizes semiconductor design by enabling smaller, specialized dies to be co-packaged for enhanced performance and reduced manufacturing costs, this role will be instrumental in defining architectures that   optimize   power, performance, area, and cost for MCU-class edge AI applications . Key Responsibilities   Define and drive chiplet-based architectures for edge AI microcontroller platforms, including specification of chiplet boundaries, interfaces, power domains, and integration strategies that   optimize for   cost, performance, and manufacturability.   Collaborate closely with the   analog   business unit to align on chiplet definitions, die-to-die interface specifications, packaging requirements, and integration roadmaps ensuring consistency across platform and product lines.   Perform comprehensive architectural trade-off analysis to   optimize   power, performance, area, and cost for MCU-class products,   utilizing   modeling, simulation, and benchmarking to   validate   design decisions against product requirements.   Conduct advanced-node product research, feasibility studies, and technology definition activities including evaluation of process capabilities, design rule impacts, and technology-specific optimization opportunities for edge AI workloads.   Develop and   optimize   end-to-end advanced-node design flows for high-volume MCU products, working with EDA vendors and internal CAD teams to   establish   robust methodologies for synthesis, placement, routing, timing closure, and verification.   Work cross-functionally with AI accelerator, CPU core, memory subsystem, embedded software, advanced packaging, and manufacturing teams to ensure holistic system optimization and successful product delivery.   Support architecture reviews, technical alignment meetings, and product definition milestones by preparing technical presentations, documentation, and recommendations for executive and engineering audiences.   Provide technical leadership and mentorship to junior engineers within the MCU and Edge AI engineering teams, fostering a culture of innovation, technical excellence, and continuous learning.   Requirements/Qualifications: Required Qualifications Bachelors Degree in Electrical or Computer Engineering (or similar degree),   Masters Degree   preferred. Minimum of 10+ years of relevant experience with Verilog/ SystemVerilog   and/or VHDL. Strong knowledge of chiplet-based or modular architectures and system-level integration, including understanding of die-to-die interconnect standards and 2.5D integration techniques. Hands-on experience with advanced-node   FinFET   technology nodes and associated design flows. Possess   excellent analytical and problem-solving skills. E xcellent communication and documentation skills (verbal and written). Proficiency   with EDA tools for architecture exploration, RTL design, synthesis, and physical implementation. Experience with hardware description languages (Verilog,   SystemVerilog , VHDL) and scripting languages (Python,   Tcl , Perl) for design automation. Preferred Qualifications   Experience working with cross-business-unit teams on shared IP, chiplet definitions, or platform architectures. Background in edge AI acceleration, digital signal processors, or embedded machine learning inference engines. Proven   track record   in high-volume, cost-sensitive MCU product development from architecture definition through production. Familiarity with silicon bring-up, validation, debug, and production lifecycle support activities. Knowledge of UCIe (Universal Chiplet Interconnect Express) or other chiplet interface standards and their implementation. Experience with advanced nodes (e.g., 7nm-class and beyond) and roadmap planning. Travel Time: 0% - 25% Physical Attributes: