Optical Hardware Systems Test Engineer

The application window is expected to close on: 10/01/2026 Meet the Team Cisco ASIC Engineers develop and work with Next Generation Technology to build Cisco ASIC products keeping in mind the user experience and in accordance with IEEE standards, and industry procedures. ASIC Engineers serve a range of roles at Cisco from IP Creators and architects creating industry standards, to Solution Integrators driving multi-functional teams to go from concept to production, as well as providing expertise in Solution Verification and ensuring that our products meet Cisco and Industry quality standards. They drive innovation across the large CISCO portfolio, including but not limited to System/Board Design, Circuit Board Layout, Hardware Automation, Validation and Test, Signal Integrity and Power Design. They work multi-functionally with system designers, diagnostics engineers, customer escalation engineers, & external vendors to ensure robust test methodology & timely issue mitigation resulting in high product quality and enable next generation solutions. They drive innovation across Cisco's hardware portfolio and enable next generation solutions through IP development, research, and challenging the status quo within the industry (finding ways to optimize cost, performance, and quality). Your Impact Cisco Systems is seeking an Optical Hardware Systems Test Engineer to validate and ensure the quality of next-generation networking platforms, including switches, routers, and data center systems. What You'll Do In this high impact role, you will be hands-on in the lab leading the testing, validation, and bring-up of next-generation networking systems integrating ultra-high-speed silicon and advanced optics. You will play a pivotal role in validating ground breaking 112G/224G PAM4 SerDes channels, high-density Data Center Interconnects (DCI), and emerging Co-Packaged Optics (CPO) architectures. Lead hands-on bring-up, validation, and characterization of Silicon One ASICs integrated with high-speed optical transceivers and emerging Co-Packaged / Near-Packaged Optics (CPO/NPO) engines. Measure and characterize high-speed electro-optic channels across 112G/224G PAM4 SerDes and optical links, evaluating eye quality, bit error rate (BER), and link margins. ·Develop and maintain Python, C/C++ or similar language test automation scripts and programs to control high-speed lab equipment (oscilloscopes, BERTs, optical spectrum analyzers, power meters) and automate test workflows. Perform system stress testing across temperature, voltage, and traffic corners to ensure link stability and operating margins under full system loads. Debug and root-cause sophisticated hardware, signal integrity, and optical link issues during prototype bring-up and system validation. Partner multi-functionally with ASIC architecture, signal integrity, board design, software/diagnostics, and manufacturing teams from early silicon bring-up through production release. Who You Are You are a curious, dedicated hardware engineer who thrives in a lab environment. You enjoy solving challenging system-level problems and bridging the gap between high-speed silicon and optical interconnects. Minimum Qualifications: Bachelor’s degree in Electrical engineering, Photonics, Computer Engineering, or related technical field with 7+ years of relevant industry experience (or Master's with 4+ years, PhD with 1+ years). Hands-on experience in lab bring-up, system-level validation, and hardware testing of high-speed networking systems or electro-optic hardware. Strong understanding of optical transceivers, optical link budgets, high-speed SerDes (56G/112G+ PAM4), and bit error rate testing. Experience using standard lab instrumentation (VNAs, TDR, sampling scopes, BERTs, optical power meters, spectrum analyzers). Preferred Qualifications: Familiarity with Co-Packaged Optics (CPO), Near-Packaged Optics (NPO), or Linear Pluggable Optics (LPO). Deep Expertise with high-speed interfaces, Ethernet standards (IEEE 802.3 400G/800G), PCIe and optical transceiver management interfaces. Experience with thermal characterization of high-power silicon using liquid cooling plates, thermal chambers, or automated handlers. Prior experience with Cisco Silicon One or high-performance data center switching architectures. Proficiency in Python scripting for lab test automation, instrument control, and data analysis. Analytical Tools: Experience with JMP, Tableau, Python based AI/ML models for advanced analytics. Strong analytical, troubleshooting, and multi-functional communication skills. SiOps Why Cisco?  At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.  We are Cisco, and our power starts with you.  Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full sa