IO and Memory Sub-Sytem Architecture

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Principal Engineer to join our MIC team in San Jose, CA. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.   As a Senior Principal Architect of Memory & IO Sub-system, you’ll play a pivotal role in leading the architecture, design, and development of next generation of DRAM sub-system solutions for server and high-performance computing applications. In this full-time role, you’ll report directly to our VP of Engineering. Our Memory Interface Division is dedicated to developing all products related to Server and Client Memory Modules, and your contributions will be instrumental in developing solutions DDR6/LPDDR6/HBM solutions for Server and Client systems.   Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.   Responsibilities Lechnical Leadership   Lead the architecture, design, and development of next generation of memory subsystem solutions.  Drive technical decisions related to memory interfaces, PHY architecture, signal & power integrity, and system integration.  Define subsystem requirements and translate system-level needs into architecture and design specifications.  Provide technical leadership across multidisciplinary teams including ASIC, PHY, firmware, validation, system architecture, and platform engineering.  Memory Subsystem Development   Develop expertise-driven solutions involving:   DDR4/5/6, LPDDR4/5/6, HBM3/4/5 DRAM  DDR4/5/6 Registered Clock Driver (RCD)  DDR4/5/6 Data Buffer (DB)  DDR4/5/6 DIMMs (RDIMM/LRDIMM/MRDIMM)  DDR4/5/6 Server Platforms  Analyze memory subsystem performance, timing, power, and interoperability requirements.  Drive systems bring-up, debug, characterization, and performance optimization activities.  PHY Architecture and Design   Define and review high-speed PHY architectures for next-generation memory and interface products.  Develop and optimize:   Transmitter (Tx) architectures  Receiver (Rx) architectures  Clocking and timing circuits  Equalization schemes including DFE, CTLE, and related signal-conditioning techniques  Evaluate signal integrity challenges and develop solutions to improve channel performance and margin.  Digital Design and Verification   Contribute to digital design, architecture reviews, and RTL implementation strategies.  Define verification methodologies and coverage requirements.  Lead debugging and root-cause analysis of complex design and system-level issues.  Collaborate with validation teams to ensure robust product functionality and compliance.  Specification and Customer Engagement   Develop and maintain architecture specifications, design requirements, and technical documentation.  Present technical proposals, design reviews, and architecture recommendations to engineering leadership, customers, and ecosystem partners.  Translate JEDEC and industry standards into product requirements and implementation guidelines.  Participate in customer discussions, technical reviews, and interoperability initiatives.  Qualifications Education   Master’s Degree (M.S.) in Electrical Engineering, Computer Engineering, or a related technical discipline.  Experience   12+ years of industry experience in semiconductor, ASIC, memory, or high-speed interface development.  Demonstrated experience leading complex technical projects and influencing architectural decisions.  Key Competencies   System Architecture Leadership  DDR5/DDR6/LPDDR5/HBM Memory Expertise  High-Speed PHY Design  Tx/Rx Circuit Architecture  DFE/CTLE Equalization Techniques  I2C, I3C, USB Interfaces  Digital Design & Verification  Technical Specification Development  Analytical Problem Solving  Executive-Level Presentations  About Rambus   Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.   Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.   The US salary range for this full-time position is $180,000 to $334,200. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.  At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work.   Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an indi