ASIC Subsystem Engineer (Mid-level or Lead)

ASIC Subsystem Engineer (Mid-level or Lead) Company: The Boeing Company The Boeing Space & Missions Systems Division is seeking a Mid-level or Lead ASIC Subsystem Engineer to join the Space and Launch Engineering team in El Segundo, California. In this role, you will support the design and development of advanced ASICs and mixed-signal components for space-based digital communication systems supporting commercial, civil, and national security programs. You will work with a highly motivated, multidisciplinary team and collaborate with domestic and international customers, suppliers, program management, integration and test engineers, and senior technologists. Assignments may span the full unit life cycle, including architecture development, internal trade studies, concept studies, system definition, design development, verification, integration, qualification, and unit sell-off. This position is primarily focused on subsystem-level architecture, requirements, verification, integration, and technical coordination for ASICs, digital signal-processing functions, and mixed-signal ADC/DAC converters. This position is expected to be 100% onsite.  The selected candidate will be required to work onsite at the El Segundo, CA, location. This worksite participates in Boeing’s optional 9/80 schedule rotation. 9/80 is a rotation in which employees can work 9 hour shifts, 8 days per pay period (bi-weekly) and receive every other Friday off. Position Responsibilities: Define, develop and validate next-generation multi-ASIC architectures incorporating digital signal-processing cores for digital communication subsystems. Architect, derive, allocate, and verify requirements for ASIC functions, interfaces, and subsystem performance. Develop general verification strategies and requirements traceability for ASIC and mixed-signal functions. Lead technical trade studies involving performance, cost, schedule, risk, complexity, and manufacturability. Serve as a subsystem engineering point of contact for ASIC design houses, IP suppliers, semiconductor manufacturers, and internal engineering organizations. Coordinate technical activities, analyses, reviews, and deliverables within the ASIC integrated product team. Derive and validate ADC/DAC performance requirements, including parameters such as: ENOB, SNR, SINAD, SFDR, THD, Aperture and clock jitter, linearity, gain and and offset errors, spurs, calibration, synchronization; all with considerations of performance over process, voltage and temperature operating conditions Signal-to-noise ratio Develop and manage design validation test plans for mixed-signal ADC/DAC converters. Define and manage screening requirements and screening plans for mixed-signal components. Support subsystem-level modeling, analysis, integration, and performance simulations for ADC/DAC converters and related ASIC functions. Support ASIC-level and subsystem-level hardware and software integration. Support hardware procurement, supplier technical reviews, design reviews, qualification activities, and unit sell-offs. Prepare technical presentations, review materials, requirements documentation, interface documentation, verification evidence, and technical reports. Identify technical risks and develop mitigation plans in coordination with program and engineering leadership. Basic Qualifications (Required Skills and Experience): This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. A final U.S.Secret Clearance Post-Start is required. Bachelor of Science degree in engineering, engineering technology (includes manufacturing engineering technology), chemistry, physics, mathematics, data science, or computer science. 5 or more years' related work experience or an equivalent combination of technical education and experience. Experience with a higher-level programming code (e.g. C, MATLAB, Python, or similar). 1+ years of experience working with analog/mixed-signal/digital circuits. 1+ years of experience developing digital architecture requirements, interfaces, verification plans, or related system requirements. 1+ years of experience with ASIC development processes and experience working with ASIC manufacturers or ASIC design houses and IP suppliers. Preferred Qualifications (Desired Skills / Experience): Master’s degree or higher in Electrical Engineering, Computer Engineering, or a related technical discipline (a master’s degree may count as two years of experience, where applicable). Three or more years of experience in VLSI, digital architecture or verification planning for digital-communications ASICs. Three or more years of subsystem or systems engineering experience involving digital communication or radar payloads. Nine or more years of cumulative experience in engineering roles related to the responsibilities described above. Experience developing architecture, requirements, and verification plans for ASICs, ADCs, DACs, or related mixed-signal components. Experience with built-in test or built-in self-test functions for ASIC verification. Experience with high-speed interfaces (i.e. JESD or other SerDes multi-lane interfacing standards), general control interfaces (SPI, I2C, JTAG derivatives), SerDes IP procurement. Experience procuring and evaluating SerDes and ADC/DAC IP. Experience tracing requirements from system specifications or architecture descriptions to ASIC-level requirements. Experience documenting requirement allocation rationale and validation evidence. Experience supporting ASIC design reviews, supplier reviews, hardware integration, qualification, and unit sell-off. Demonstrated ability to lead technical activities and collaborate effectively in multidisciplinary, team-oriented environments. Level 4 (Lead): 9 or more years' related work experience or an equivalent combination of technical education and experience. Confl